Innovative Research Award
Reza Kazerooni-Zand — University of Tehran
Reza Kazerooni-Zand is an University of Tehran whose published work addresses hardware architectures for artificial intelligence, particularly mixed-signal and memristor-based approaches to accelerating deep neural network inference. His documented publications examine coarse-grained reconfigurable architectures, in-memory computation, reliability, energy efficiency, and hardware support for convolutional neural networks, providing a research profile situated at the intersection of AI, computer architecture, and VLSI design.[1][2]
Abstract
Reza Kazerooni-Zand is a researcher in artificial intelligence hardware whose publications investigate mixed-signal computing, memristive architectures, coarse-grained reconfigurable architectures, and efficient deep neural network inference. His research connects analog dot-product computation with digital processing, memory hierarchy, reliability mechanisms, and configurable hardware structures. Published studies describe architectures intended to improve computational throughput while addressing energy consumption and device-level reliability concerns. His documented work includes research on memristor-based acceleration of convolutional neural networks and mixed-signal CGRAs, with recent work extending this direction toward reliable high-speed inference. These contributions position his publication record within contemporary AI accelerator and VLSI research.[1][2]
Keywords
Memristive computing, mixed-signal computing, coarse-grained reconfigurable architecture, deep neural network inference, convolutional neural networks, AI accelerators, in-memory computing, hardware acceleration, VLSI design, energy-efficient computing, reliable computing, fault-tolerant architecture, analog computing, digital computing, and neuromorphic hardware.[1][2]
Introduction
Reza Kazerooni-Zand’s research addresses an important engineering problem created by increasing computational demands from deep learning: improving inference performance without proportionally increasing hardware cost and energy consumption. His publications investigate mixed-signal architectures that combine analog computation with digital control, using memristive crossbars and reconfigurable processing structures to support neural-network workloads. This work is documented in ACM and Elsevier-indexed publications.[1][2]
Research Profile
Reza Kazerooni-Zand develops research around AI accelerator hardware, with particular attention to mixed-signal computation and memristive technologies. His documented work combines coarse-grained reconfigurable architectures with analog dot-product operations and digital processing elements, while considering memory movement, configurability, reliability, and energy efficiency. These themes connect circuit-level technologies with system-level neural-network acceleration requirements.[1]
Research Contributions
Reza Kazerooni-Zand contributes to research on mixed-signal CGRAs for deep neural networks by examining analog dot-product computation, memristor crossbars, configurable processing, and data movement. His later publication further addresses reliability through mechanisms for detecting and correcting memristor faults while accelerating convolutional neural-network inference. Together, these studies demonstrate continuity between performance-oriented and reliability-oriented accelerator research.[1][2]
Publications
Reza Kazerooni-Zand has documented publications in the area of neural-network accelerator architecture. His 2023 ACM Transactions on Design Automation of Electronic Systems article, co-authored with Mehdi Kamal, Ali Afzali-Kusha, and Massoud Pedram, presents a memristive mixed-signal CGRA for DNN inference. A 2026 Neurocomputing article extends this research toward reliable, high-speed CNN inference acceleration using memristor-based mixed-signal architecture.[1][2]
Research Impact
Reza Kazerooni-Zand’s documented research contributes to the broader study of hardware-efficient artificial intelligence by addressing computational acceleration and reliability within emerging architectures. The publication record provides evidence of peer-reviewed work in established technical venues and identifies research directions involving memristors, mixed-signal processing, neural-network inference, and reconfigurable architectures. Citation and bibliographic indicators may change as databases are updated.[1][2]
Award Suitability
Reza Kazerooni-Zand’s documented publication record provides research-based material relevant to an academic recognition category focused on innovative research. His work addresses emerging AI hardware through mixed-signal computing, memristive processing, configurable accelerator architectures, and reliability techniques. Any award determination remains dependent on the applicable criteria, nomination requirements, independent review, and comparative assessment established by the organizing body.[1][2]
Conclusion
Reza Kazerooni-Zand’s research profile is centered on hardware architectures for artificial intelligence, particularly mixed-signal and memristive approaches to neural-network acceleration. His publications document work spanning DNN inference, CNN acceleration, CGRAs, analog computation, memory-centric processing, and hardware reliability. The record offers a focused example of contemporary research connecting emerging device technologies with practical AI computing architectures.[1][2]
External Links
References
- Kazerooni-Zand, Reza; Kamal, Mehdi; Afzali-Kusha, Ali; Pedram, Massoud. (2023). Memristive-based Mixed-signal CGRA for Accelerating Deep Neural Network Inference. ACM Transactions on Design Automation of Electronic Systems, 28(4), 66:1–66:25.
https://doi.org/10.1145/3595638
- Kazerooni-Zand, Reza; Afzali-Kusha, Ali; Kamal, Mehdi. (2026). Reliable yet high-speed memristor-based mixed-signal coarse-grained reconfigurable architecture for CNN inference acceleration. Neurocomputing, 688, 133773.
https://doi.org/10.1016/j.neucom.2026.133773
- DBLP. (n.d.). Bibliographic record for Memristive-based Mixed-signal CGRA for Accelerating Deep Neural Network Inference. Computer Science Bibliography.
https://dblp.org/rec/journals/todaes/KazerooniZandKAP23
- ORCID. (n.d.). Reza Kazerooni-Zand, ORCID.
https://orcid.org/0009-0005-9465-2265
- Elsevier. (n.d.). Scopus author details: Reza Kazerooni-Zand, Scopus.
https://www.scopus.com/authid/detail.uri?authorId=60561887500